1. Field of the Invention
This invention relates to a decoder circuit for decoding an address signal in a semiconductor memory device, and more particularly to a decoder circuit having a decoded output driving CMOS inverter circuits.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing part of a cell array and part of a memory cell array of the conventional mask ROM (read only memory). 61 indicates memory cells each constructed by an enhancement or depletion MOS transistor corresponding to write data "1" or "0" 62 indicates memory cell blocks each having a plurality of memory cells 61 (in this example, eight memory cells) connected in a form of a NAND logic circuit, 63 indicates block selecting enhancement MOS transistors, 64 indicates block selecting depletion MOS transistors, 65 indicates block selecting lines, 66 indicates word lines, 67 indicates a main row decoder constructed by a NAND gate, and 68 indicates a block selecting NOR gate to which one of block selection signals .phi.si (i=1, 2, 3, 4) and an output of the main row decoder are input. Further, 69 indicates word line selecting NOR gates each of which is supplied with one of word line selection signals .phi.wi (i=1, 2, 3, - - - , 8) and an output of the main row decoder, and 70 indicates word line driving CMOS inverters each having an input connected to an output of one.
Generally, since the pitch of the word lines 66 is relatively small in the NAND mask ROM, it becomes difficult to drive the individual word lines by use of the respective word line driving circuits when taking the pattern layout into consideration, and usually, the ROM is constructed to drive the two or four word lines by use of one word line driving circuit. Further, the word line driving circuit must be made simple in construction 10 when taking the pattern layout into consideration, and for this reason, the CMOS inverters 70 are used as the word line driving circuit. However, in this case, it becomes necessary to connect the NOR gates 69, which are used as the pre-drivers, at the preceding stage of the CMOS inverters.
Further, in order to reduce the number of contacts between the memory cell blocks 62 and bit lines 71 in the above NAND type mask ROM, each bit line contact is commonly shared by corresponding four of the memory cell blocks 62. In order to permit a desired one of the four memory cell blocks 62 to be selected, a block selection enhancement transistor 63 and depletion transistor 64 are serially connected between one end of each of the four memory cell blocks 62 and the bit line contact so that the other end of each of the four memory cell blocks 62 may be selectively connected to a ground node.
At the time of reading out data from the above NAND type mask ROM, if an output of the main row decoder 67 is set to the "L" level and one of the block selection signals .phi.si (i=1, 2, 3, 4) is set to the low level "L" (the remaining three block selection signals are kept at the high level "H"), then an output of a corresponding one of the block selection NOR gates 68 (that is, one of the NOR gates 68 which is supplied with the block selection signal .phi.si of "L" level) is set to the "H" level and outputs of the remaining three NOR gates 68 are kept at the "L" level. As a result, a corresponding one of the four memory cell blocks 62 sharing one bit line contact (that is, one of the memory cell blocks 62 which receives "H" and "L" level outputs from the corresponding NOR gates 68) is selected and the remaining three memory cell blocks 62 are not selected. When one of the word line selection signals .phi.wi (i=1, 2, - - - , 8) is set to the "L" level (the remaining seven word line selection signals are kept at the "H" level), then an output of a corresponding one of the word line selection NOR gates 69 (that is, one of the NOR gates 69 which is supplied with the word line selection signal .phi.wi of "L" level) is set to the "H" level and outputs of the remaining seven NOR gates 69 are kept at the "L" level. As a result, an output (selected output) of a corresponding one of the CMOS inverters 70 (that is, one of the CMOS inverters 70 which receives "H" and "L" level outputs from the corresponding NOR gates 69) is set to the "L" level and outputs (non-selected outputs) of the remaining seven CMOS inverters are kept at the "H" level.
Therefore, seven non-selected cells among the eight memory cells 61 in the selected memory cell block 62 are turned on and the remaining one selection cell is turned off or on according to whether it is of enhancement type or depletion type. As a result, a readout output of "H" or "L" level is derived from the selected memory cell block 62 according to the write-in data of the selected cell.
However, with the above construction, since the pattern area of the NOR gates 69, which are arranged at the preceding stage of the CMOS inverter and are also used as pre-drivers, and the pattern area of the output wiring region 72 for the NOR gates are relatively large, the area occupied by the row decoder on the chip becomes relatively large, thereby making it difficult to reduce the chip size.
As described above, when the conventional decoder circuit is constructed in such a pattern that decoder output lines may be driven by a plurality of CMOS inverters on the semiconductor chip, it is necessary to arrange pre-driver circuits at the preceding stage of the plurality of CMOS inverters, and as a result, the pattern areas of the pre-driver circuits and the output wiring region for the pre-driver circuits become relatively large and the area occupied by the decoder circuit on the semiconductor chip becomes large, thus making it difficult to reduce the chip size.